1. Field of the Invention
The invention relates generally to integrated circuits and more specifically to a method and an apparatus for removing a particle from a portion of a metal plug on a substrate.
2. Description of Related Art
Integrated circuits are made up of literally millions of active devices formed in or on a silicon substrate or well. The active devices that are initially isolated from one another are later connected together to form functional circuits and components. The devices are interconnected together through the use of well known multilevel interconnections. A cross-sectional illustration of a typical multilevel interconnection structure 10 is shown in FIG. 1. Interconnection structures normally have a first layer of metallization, an interconnection layer 12 (typically aluminum alloys with up to 3% copper), a second level of metallization 14, and sometimes a third or even fourth level of metallization. Interlevel dielectrics 16 (ILDs), such as doped and undoped silicon dioxide (SiO2), are used to electrically isolate the different levels of metallization in silicon substrate or well 18. The electrical connections between different interconnection levels are made through the use of metallized vias 11 formed in ILD 16. In a similar manner, metal contacts 22 are used to form electrical connections between interconnection levels and devices formed in well 18. The metal vias 11 and contacts 22, hereinafter being collectively referred to as “vias” or “plugs”, are generally filled with tungsten 13 and generally employ an adhesion layer 15 such as TiN. Adhesion layer 15 acts as an adhesion layer for the tungsten metal layer 13 which is known to adhere poorly to SiO2. At the contact level, the adhesion layer acts as a diffusion barrier to prevent W and Si from reacting.
In one process, metallized vias or contacts are formed by a blanket tungsten deposition and a chemical mechanical polish (CMP) process. In a typical process, via holes 23 are etched through an ILD 24 to interconnection lines or a semiconductor substrate 26 formed below as shown in FIG. 2a. Next, a thin adhesion layer 28, such as TiN, is generally formed over ILD 24 and into via hole 23, as shown in FIG. 2b. Next, a conformal tungsten film 29 is blanket deposited over the adhesion layer and into the via hole 23. The deposition is continued until the via hole 23 is completely filled with tungsten. Next, the metal films formed on the top surface of ILD 24 are removed by CMP, thereby forming metal vias or plugs 28.
In a typical CMP process as shown in FIG. 2c, the substrate or wafer 30 is placed face-down on a polishing pad 32 which is fixedly attached to a rotatable platen 34. In this way, the thin film of a metal layer to be polished (i. e., tungsten film 29) is placed in direct contact with pad 32. A carrier 36 is used to apply a downward pressure F1 against the backside of substrate 30. During the polishing process, pad 32 and platen 34 are rotated while a downward force is placed on substrate 30 by carrier 36. An abrasive and chemically reactive solution, commonly referred to as “slurry” 35 is introduced onto pad 32 during polishing. Slurries generally include an abrasive material such as alumina or silica. The slurry initiates the polishing process by chemically reacting with the film being polished. The polishing process is facilitated by the rotational movement of pad 32 relative to wafer 30 as slurry is provided to the wafer/pad interface. Polishing is continued in this manner until all of the film on the insulator is removed.
After polishing, the substrate is generally rinsed with a solution such as deionized water in order to remove particles that remain on the substrate after the CMP operation. Conventional rinsing methods include using a scrubber with deionized water. However, high-speed spin rinse generally does not remove all of the particles. Another conventional method is a “magasonic” bath that involves high frequency vibration in which particles are shaken off the substrate. This method also leaves particles on the metal layer.
To properly form multiple layers of interconnect and to increase die yield, it is necessary to reduce particles that may block electrical conduction from one metal layer to another metal layer. If a particle is on a via, there is no electrical connection between the area where the particle is located and the metal layer. Accordingly, removing as many particles from a metal layer reduces the failures that may occur in an integrated circuit.
Another way in which the integrity of the metal layer may be affected relates to the removal of the metal layer during the polishing process. In removing particles, it must be ensured that a metal layer is not removed to a level such that a gap exists between a metal layer subsequently deposited onto the via or contact which may affect electrical conduction between the metal layer and the via.
Despite advances that have been made in removing particles from metallized plugs in contacts and vias, there are still failures that occur in integrated circuits due to inadequate removal of particles from a metal layer. It is therefore desirable to have a method that efficiently removes particles from a metal layer and simplifies the conventional processes used.